The invention relates to delay locked loops (DLLs), and more particularly, to a DLL capable of preventing false lock and a related method of preventing false lock in a DLL.
Delay locked loops (DLLs) are a common circuit component used to produce a plurality of delay locked signals having equal frequency but different phase relationships with respect to an incoming clock signal. Please refer to FIG. 1. FIG. 1 shows a block diagram of a DLL 100 according to the related art. As shown in FIG. 1, the DLL 100 includes a phase detector (PD) 150, a charge pump 150, a loop filter 170, and a delay line 190. An incoming clock signal CKIN (having a period of T) is input to the DLL 100, and a voltage control signal Vctrl generated by the DLL 100 is used to control delay stages in the delay line 190. In this example, the delay line 190 has a total of N delay stages connected in series (not shown), the mth delay stage having an output delay clock of CKm (m being an integer between 1 and N). Wherein, the last delay stage produces a delay clock CKN lagging the input signal CKIN by a delay lag of Td. The PD 150 receives the incoming clock signal CKIN and delay clock CKN as inputs and compares their phases to generate an upward adjustment signal UP or a downward adjustment signal DOWN according to the phase difference. By controlling the charge pump 160, the upward adjustment signal UP and the downward adjustment signal DOWN, via the loop filter 170, adjust the value of the control voltage Vctrl to either increase or decrease the delay lag Td between delay clock CKN and the incoming clock signal CKIN.
Theoretically speaking, the operational result of the DLL 100 is that the control voltage Vctrl will be controlled to a value that allows the last delay stage in the delay chain 190 to produce a delay clock CKN that lags the incoming clock signal by a delay lag Td equal to the value of T. Therefore, if the delay lag Td is not equal to T, the upward adjustment signal UP and the downward adjustment signal DOWN will adjust the value of the control voltage Vctrl to the appropriate value via the loop filter 170.
Please refer to FIG. 2 and FIG. 3 showing signal diagrams of a traditional DLL during normal operations. In FIG. 2, delay clock CKN lags the incoming clock signal CKIN by a delay lag of Td being between 1 T and 1.5 T. During locking operations of the DLL, the rising edge of delay clock CKN is adjusted toward the nearest rising edge of the incoming clock signal CKIN. Because of this, the traditional DLL corrects delay clock CKN in the direction shown by arrow 210 (thereby decreasing the delay lag Td) until the final result is that delay clock CKN is locked with a delay lag of Td=1 T. In FIG. 3, delay clock CKN lags the incoming clock signal CKIN by a delay lag of Td being between 0.5 T and 1 T. During locking operations of the DLL, the rising edge of delay clock CKN is adjusted toward the nearest rising edge of the incoming clock signal CKIN. Because of this, the traditional DLL corrects delay clock CKN in the direction shown by arrow 310 (thereby increasing the delay lag Td) until the final result is that delay clock CKN is locked with a delay lag of Td=1 T.
However, using the traditional DLL, delay clock CKN must lag the incoming clock signal CKIN by a delay lag Td being between 0.5 T and 1.5 T before the DLL will enter normal operations as shown in FIG. 2 and FIG. 3. If the delay lag Td is less than 0.5 T or greater than 1.5 T, the traditional DLL will enter a false locked condition. Please refer to FIG. 4 and FIG. 5 showing signal diagrams of a traditional DLL under false locking conditions. In FIG. 4, delay clock CKN lags the incoming clock signal CKIN by a delay lag Td being less than 0.5 T. During locking operations of the DLL, the rising edge of delay clock CKN is adjusted toward the nearest rising edge of the incoming clock signal CKIN as shown by arrow 410 (thereby decreasing the delay lag Td). But, in actuality, delay clock CKN should lag the incoming clock signal CKIN on the time axis. Although the delay lag Td could be decreased, in practice it cannot be decreased to zero. Therefore, a situation is produced in which when Td is decreased to a certain degree, even if the DLL continues to attempt to decrease Td, there is no further decrease in Td. That is, it is not possible to smoothly lock delay clock CKN at Td=0 T. This situation is referred to as stuck locking. In FIG. 5, delay clock CKN lags the incoming clock signal CKIN by a delay lag Td being greater than 1.5 T. During locking operations of the DLL 100, the rising edge of delay clock CKN is adjusted toward the nearest rising edge of the incoming clock signal CKIN as shown by arrow 510 (thereby increasing the delay lag Td). This results in the delay clock CKN being erroneously locked with a delay lag Td=K·T, where K is an integer greater than 1 (e.g., in FIG. 5, Td=2 T). This situation is referred to as harmonic locking.
The above mentioned stuck locking and harmonic locking situations both prevent the DLL 100 from locking with the desired delay lag of Td=T and, therefore, result in a false locked condition. A problem with the traditional DLL is that it is unable to eliminate false locked conditions.